Conventionally, the process of using feedback to attenuate the level of additive noise and distortion in a particular frequency band, without attenuating the level of a signal in the same frequency band, is referred to as noise shaping. Use of feedback to combine a corrupted output signal (i.e., an impaired output signal) with an input reference signal, followed by subsequent processing, causes unwanted signal impairments to be filtered with one transfer function (i.e., a noise-transfer-function) while a desired input signal is filtered with a different transfer function (i.e., a signal-transfer-function). In effect, noise and distortion are shifted (i.e., shaped by the noise-transfer-function) into frequencies that lie outside the band of an input signal (e.g., the band determined by the single-transfer-function). The processing that produces this noise-shaped response is sometimes referred to as modulation, and the circuitry associated with this processing, is sometimes referred to as a modulator. Common instantiations of noise shaping include phase-locked loops (PLLs) for frequency synthesis, and delta-sigma (ΔΣ) modulators for data conversion.
Circuit 10A, illustrated in FIG. 1A, is an exemplary PLL of the type conventionally used for shaping the phase noise which corrupts the output of a voltage-controlled oscillator (VCO). The PLL of circuit 10A produces an output signal (i.e., a version of the input signal) with a frequency (fOUT) that is N times greater than the frequency (fREF), where N is an integer determined by the operation of a frequency divider in the feedback path (e.g., frequency divider 15). In circuit 10A, the phase variation (noise) at the output 3A of VCO 13 is fed back to phase detector 7A (e.g., as signal 6A from frequency divider 15), where it is combined with reference input 1A. Second-order integration within loop filter 9A (i.e., including implicit frequency-phase integrator 21), results in a (phase) noise-transfer-function HNTF (i.e., the transfer function to output 3A of PLL 10A, from a virtual point of noise addition within VCO 13) which is of the form
                    H        NTF            ⁡              (        s        )              =                  s        2                              s          2                +                  2          ⁢                                          ⁢          ζ          ⁢                                          ⁢                                    ω              n                        ·            s                          +                  ω          n          2                      ,where the coefficients of loop filter 9A determine the natural frequency ωn and the damping factor ζ of the PLL. A typical plot of the noise-transfer-function (NTF) for a conventional PLL (e.g., circuit 10A) is curve 31 of FIG. 1B. As illustrated in FIG. 1B, the phase noise of the VCO is shaped with a high-pass response, such that phase noise is attenuated at frequencies less than ωn. In contrast, the same processing results in a signal-transfer-function HSTF, from input 2 of the PLL to output 3A of the PLL, which is of the form
            H      STF        ⁡          (      s      )        =                              2          ⁢                                          ⁢          ζ          ⁢                                          ⁢                                    ω              n                        ·            s                          +                  ω          n          2                                      s          2                +                  2          ⁢                                          ⁢          ζ          ⁢                                          ⁢                                    ω              n                        ·            s                          +                  ω          n          2                      .  The signal-transfer-function (STF) for circuit 10A produces a low-pass response, such as curve 32 of FIG. 1B. At the output of the PLL, therefore, noise shaping causes the phase variation (i.e., noise) of the VCO to be filtered with one transfer function (i.e., a high-pass response), and the phase variation (i.e., signal) of the reference input to be filtered with a different transfer function (i.e., a low-pass response).
Conventional delta-sigma modulators are circuits 10B&C, which are illustrated in FIGS. 2A&B, respectively. Modulators 10B&C operate on continuous-time input signals, and therefore, are referred to as continuous-time delta-sigma (CT-ΔΣ) modulators. Conventional CT-ΔΣ modulators produce a coarsely quantized version (e.g., digital signals 3B&C) of a continuous-time input signal (e.g., analog signal 1B), using a sampling rate which is many times the bandwidth of the input signal (i.e., the input signal is oversampled). As shown in FIGS. 2A&B, conventional CT-ΔΣ modulators include: 1) an input combining operation (e.g., within subtractor 7B); 2) an integration function of second-order (e.g., within loop filter 9B&C); 3) a rounding/truncation function (e.g., within quantizer 14); and 4) a feedback digital-to-analog (D/A) conversion function (e.g., within D/A converter 17). A variation of the CT-ΔΣ modulator is the discrete-time delta-sigma (DT-ΔΣ) modulator, which includes a sample-and-hold function at the modulator input, such that the modulator operates on discrete-time signals. Referring to FIGS. 2A&B, modulators 10B&C produce a (quantization) noise-transfer-function HNTF (i.e., a transfer function to outputs 3B&C of modulators 10B&C, from a virtual point of noise addition within quantizer 14) which is of the form
                    H        NTF            ⁡              (        s        )              =                  s        2                              s          2                +                  2          ⁢                                          ⁢          ζ          ⁢                                          ⁢                                    ω              n                        ·            s                          +                  ω          n          2                      ,and produce a signal-transfer-function HSTF (i.e., a transfer function from input 1B to outputs 3B&C of modulators 10B&C) which is of the form
            H      STF        ⁡          (      s      )        =                    ω        n        2                              s          2                +                  2          ⁢                                          ⁢          ζ          ⁢                                          ⁢                                    ω              n                        ·            s                          +                  ω          n          2                      .  The NTF produces a frequency response which is high-pass and similar to curve 31 shown in FIG. 1B, while the STF produces a frequency response that is low-pass and similar to curve 32 shown in FIG. 1B. Instead of attenuating low-frequency phase noise that is introduced at the output of a VCO, conventional ΔΣ modulators attenuate low-frequency quantization noise that is introduced by a coarse quantization operation (i.e., noise from quantizer 14).
An alternative to the conventional ΔΣ modulator is the Diplexing Feedback Loop (DPL) circuit 10D, shown in FIG. 2C. Like a conventional ΔΣ modulator, DPL circuit 10D produces an oversampled and coarsely quantized version of a continuous-time input signal (e.g., analog signal 1B), such that the quantization noise introduced by the coarse quantization operation (e.g., noise from quantizer 14), is attenuated in a frequency band occupied by input signal 1B. Also, the DPL is similar to a conventional ΔΣ modulator in that it does not appreciably attenuate the input signal itself. Rather than connecting the output of a combining operation (e.g., adder 7C) to the input of a coarse quantization operation (e.g., quantizer) through a loop filter (i.e., through integrators in a feed-forward path), however, the DPL shapes noise by feeding back a signal (i.e., signal 6D) which is generated through a linear combination of: 1) a filtered version of the quantizer input (i.e., quantizer input signal 4D at node 19); and 2) a filtered version of the quantizer output (i.e., quantizer output 3D). Since the DPL does not rely on active integrators or filtering in a feed-forward path, the DPL has significant performance advantages over a conventional ΔΣ modulator, including: 1) the DPL is better suited for high-frequency operation because there are no active integrators which limit processing bandwidth; and 2) the DPL has an STF which is essentially all-pass because filtering takes place within a feedback path. Referring to the block diagram shown in FIG. 2C, the linearized noise-transfer-function (NTF) of DPL 10D, is of the form
            NTF      ⁡              (        s        )              =                  1        +                                            H              1                        ⁡                          (              s              )                                ·                                    H              3                        ⁡                          (              s              )                                                  1        +                                            H              1                        ⁡                          (              s              )                                ·                                    H              3                        ⁡                          (              s              )                                      -                                            H              2                        ⁡                          (              s              )                                ·                                    H              3                        ⁡                          (              s              )                                            ,and it can be shown that for the appropriate choice of filter responses (e.g., H1, H2, and H3), DFL 10D produces a second-order noise-shaped response that is comparable to that of a conventional ΔΣ modulator. More specifically, an appropriate choice for the filter responses is:H1(s)·H3(s)=φ00·W00(s)+φ01·W01(s)H2(s)·H3(s)=φ10·W10(s)+φ11·W11(s),where φij are positive or negative scalars and Wij(s) are low-pass responses of first to fifth order. The block diagrams of FIGS. 2D&E, illustrate one method by which a second-order DPL structure (e.g., generalized modulator 10E) can be adapted to create a DPL structure which shapes quantization noise according to a fourth-order response (e.g., generalized modulator 10F).
Regardless of the intended application (e.g., the attenuation of phase noise, quantization noise, etc.) or the type of apparatus employed (e.g., PLL, ΔΣ modulator, DFL, etc.), circuits capable of wideband operation are needed for effective noise shaping at high frequencies. The distributed amplifier, shown in FIG. 3A, represents a conventional method used to extend the operating bandwidth of standard amplifier configurations (i.e., amplifiers which employ a standard form of negative feedback). In a standard configuration (e.g., transistors in a common-emitter or common-source configuration), the bandwidth and the gain of an amplifier are inversely related due to the Miller effect, which causes the capacitance of the active device to increase with increasing gain. A distributed amplifier, such as circuit 20 of FIG. 3A, overcomes the problem of gain-dependent bandwidth using a combination of two tactics: 1) to reduce the impact of the Miller effect, the outputs of multiple, low-gain amplifiers (e.g., gain cells 26A) are summed; and 2) to circumvent the problem of additive capacitance, which would otherwise limit bandwidth, the intrinsic capacitances of active devices (e.g., the input or output capacitance of the transconductance elements comprising gain cells 26A) are grouped with discrete inductors (e.g., inductors 33A) to form the reactive impedance segments (e.g., L-sections 27A&B) of an “artificial” transmission line (e.g., input transmission line 25A and output transmission line 35A). The term “artificial” transmission line is conventionally used to describe a ladder network consisting of concatenated inductor-capacitor sections (e.g., L-sections 27A&B), because such a structure approximates the general properties of an actual transmission line (e.g., characteristic impedance, propagation delay, frequency-dependent attenuation, etc.). Conventionally, artificial transmission lines are of the type illustrated by circuits 30A&B of FIGS. 3B&C, respectively. Each of circuits 30A&B is terminated in a characteristic impedance of Rterm=√{square root over (L/Cgm)}, and comprises L-sections (e.g., L-sections 27C) with series inductive reactance jω·L (e.g., from discrete inductors 33B) and shunt capacitive reactance 1/(jω·Cgm) (e.g., from discrete capacitors 34A). Circuit 30A employs a configuration where the first reactive element is a series inductor with inductance equal to ½·L, and circuit 30B employs a configuration where the first reactive element is a shunt capacitor with capacitance equal to ½·Cgm. Each L-section of circuits 30A&B, introduces a propagation delay tPD equal totPD=√{square root over (LCgm)},and overall, each circuit produces a low-pass response with a bandwidth that is approximately given by
  BW  ≈            1              π        ⁢                              LC            gm                                .  Sometimes, AC-coupling capacitors are added to the artificial transmission line, such that only AC signals are able to propagate from one end of the network to the other.
Referring again to amplifier 20 of FIG. 3A, each of the reactive impedance segments (e.g., L-sections 27A&B) consists of a series inductance (e.g., from discrete inductors 33A), which is coupled at a junction point (e.g., junction points 28A and 38A), to the intrinsic shunt capacitance at the input or output of an active device (i.e., capacitance Cgm of artificial transmissions lines 30A&B is provided by the intrinsic capacitance at the input or output of a corresponding gain cell). In amplifier 20, each reactive impedance segment (e.g., L-sections 27A&B) includes a gain (e.g., transconductance) cell, and therefore, the amplifier has a number of distributed stages n (i.e., conventionally defined as the total number of gain cells) which is equal to the total number of reactive impedance segments. Alternatively, some L-sections could comprise discrete capacitors, instead of gain cells, which would make the number of distributed stages less than the total number of reactive impedance segments. The overall bandwidth BW of amplifier 20 is independent of the number of distributed stages n, and is approximately determined by the bandwidth of each L-section according to
      BW    ≈          1              π        ⁢                              LC            gm                                ,where L is the total inductance associated with each L-section, and Cgm is the shunt capacitance associated with each L-section. Furthermore, the overall (voltage) gain AV of amplifier 20 increases linearly as the number of distributed stages increases, according to
            A      V        =                  1        2            ·      n      ·              g        m            ·              R        term              ,where: 1) n is the number of distributed stages (i.e., gain cells); 2) gm is the transconductance associated with each gain cell; and 3) Rterm=√{square root over (L/Cgm)}, is the terminating resistance for an artificial transmission line. Therefore, the gain of amplifier 20 is independent of bandwidth, and depends only on the number gain cells within the distributed ladder network (i.e., the number of distributed stages). The gain cells associated with the each of the reactive impedance segments typically are implemented using conventional topologies that include: 1) the common-source amplifier of FIG. 4A; 2) the variable-gain cascode of FIG. 4B; 3) the broadband cascode of FIG. 4C; and/or 4) the variable-gain/delay amplifier of FIG. 4D.
Conventional variations of the basic distributed amplifier (e.g., basic amplifier 20 of FIG. 3A) include cascaded distributed amplifier 50 shown in FIG. 5A, and matrix distributed amplifier 60 shown in FIG. 5B. In conventional cascaded and matrix structures, multiple artificial transmission lines are grouped together into a composite arrangement, which provides a higher overall gain for the same number of gain cells. In addition to an input transmission line (e.g., artificial transmission line 25B) and an output transmission line (e.g., artificial transmission line 35B), cascaded distributed amplifier 50 shown in FIG. 5A, also includes an intermediate transmission line (e.g., artificial transmission line 45B). Through gain cells 26B&C, intermediate transmission line 45B provides a coupling path between input transmission line 25B and output transmission line 35B. Due to the coupling of the gain cells in both a distributed arrangement (i.e., the parallel coupling of gain cells 26B across common transmission line 25B, and the parallel coupling of gain cells 26C across common transmission line 35B) and a cascaded arrangement (i.e., series coupling of the outputs of gain cells 26B to the inputs of gain cells 26C across common transmission line 45B), the voltage gain associated with cascaded amplifier 50 is given by
            A      V        =                  (                              1            2                    ·          n          ·                      g            m                    ·                      R            term                          )            m        ,where n is the number of distributed stages and m is the number of cascaded stages (e.g., m=2 for amplifier 50). As used herein, the term “distributed stages” refers to those reactive impedance segments which are linked such that: 1) the input of a gain cell associated with one L-section, is coupled in a parallel arrangement, to the input of a gain cell associated with another L-section (e.g., gain cells 26B with inputs coupled via transmission line 25B, or gain cells 26C with inputs coupled via transmission line 45B); or equivalently 2) the output of a gain cell associated with one L-section, is coupled in a parallel arrangement, to the output of a gain cell associated with another L-section (e.g., gain cells 26B with outputs coupled via transmission line 45B, or gain cells 26C with outputs coupled via transmission line 35B). The term “cascaded stages”, as used herein, refers to the number of levels through which the gain cells associated with one set of distributed stages (e.g., a first set of parallel L-sections which include gain cells 26B), is coupled in a series arrangement (i.e., inputs to outputs), to the gain cells associated with another set of distributed stages (e.g., a second set of parallel L-sections which include gain cells 26C). Like amplifier 20 of FIG. 5A, the gain of amplifier 50 is independent of bandwidth (i.e., the bandwidth depends only on the inductance and capacitance of the constituent L-sections comprising the network). More specifically, the voltage gain of amplifier 50 increases linearly with the number of distributed stages n (i.e., the number of gain cells in parallel), and increases geometrically with the number of cascaded stages m (i.e., the number of levels through which sets of distributed stages are coupled in series).
Multiple transmission lines can also be coupled via gain cells, into the matrix configuration illustrated in FIG. 5B. Compared to cascaded amplifier 50, matrix amplifier 60 of FIG. 5B, generally utilizes fewer stages to realize a particular voltage gain AV. The maximum shunt capacitance associated with any of the reactive impedance segments (e.g., the maximum shunt capacitance associated with any of L-sections 27E-G), however, is larger for the matrix configuration due to more active devices sharing a common junction point. There is a single active device at each junction point of cascaded amplifier 50 (e.g., a single active device at each of junction points 28B, 38B, and 48B), while for matrix amplifier 60, several junction points share two active devices (e.g., two active devices share each of junction points 29 and 39). Since amplifier bandwidth is inversely proportional to shunt capacitance, matrix amplifier 60 typically would have lower bandwidth than cascaded amplifier 50. Also, matrix amplifier 60 typically would have lower gain per stage than cascaded amplifier 50 because: 1) voltage gain AV is directly proportional to termination resistance Rterm; and 2) termination resistance Rterm is inversely proportional to shunt capacitance Cgm. Therefore, although the matrix configuration offers the potential benefit of fewer stages (i.e., fewer reactive impedance segments), this benefit comes at the expense of lower bandwidth and/or lower gain per stage.
In addition to amplifier circuits, distributed architectures conventionally have been utilized to implement broadband power splitters and broadband power combiners. Conventional power divider 70 shown in FIG. 6A, routes input signal 72 to two different outputs (e.g., outputs 73A&B), using: 1) a single input transmission line (e.g., artificial transmission line 75A); 2) a pair of output transmission lines (e.g., artificial transmission lines 85A&B); and 3) multiple gain cells (e.g., gm cells 26E). For identical gain cells and identical reactive impedance segments (e.g., L-sections), the ratio by which signal power is divided between the two outputs, depends on the number of stages (i.e., gain cells) associated with one of the output transmission lines relative to the other. Conversely, conventional power combiner 80 illustrated in FIG. 6B, produces a single output (e.g., output 83) by summing two different input signals (e.g., inputs 82A&B), using: 1) a pair of input transmission lines (e.g., artificial transmission lines 75B&C); 2) a single output transmission line (e.g., artificial transmission line 85C); and 3) multiple gain cells (e.g., gm cells 26F). For identical gain cells and identical reactive impedance segments, the ratio by which input signals are combined, depends on the number of stages (i.e., gain cells) associated with one of the input transmission lines relative to the other. Using similar structures, the number of output transmission lines (i.e., and gain cells) can be increased to distribute power to more than two output lines, or the number of input transmission lines (i.e., and gain cells) can be increased to combine the power from more than two input lines.
Distributed networks have been utilized to extend the operating bandwidth of conventional apparatuses that perform the functions of signal amplification, power dividing, and power combining. Distributed networks, however, have not been utilized in the design of circuits that perform the noise shaping function which is conventionally provided by phase-locked loops and delta-sigma modulators. To support advances in analog and digital signal processing speeds, therefore, the need exists for a distributed noise shaping apparatus (i.e., modulator) that offers a wider bandwidth of operation than is possible through conventional means.